Many chips operate using multiple clocks of different frequencies. Often, a chip may contain cascaded clock dividers. That is, a main clock is divided down to produce a clock at a lower clock frequency, and the clock at the lower frequency is provided to a second clock divider to divide down the clock even further. In this way, multiple clock signals at a variety of frequencies may be created and used internally to the chip.
In some implementations, a low frequency signal known as SYSREF is used to synchronize all generated clocks across of the clock dividers inside the chip. SYSREF is used to ensure that the various clock frequencies are synchronized in terms of their phases. SYSREF may be latched by a flip-flop using an input clock and the latched SYSREF is then used to synchronize the various clock dividers. For systems that include cascaded clock dividers, in which one clock divider provides the clock input to another clock divider, more than one SYSREF pulse may be used to synchronize all of the clock dividers. The latched SYSREF pulse may be periodic with all the different clocks present in the chip. Typically this is achieved by using a SYSREF pulse period which is the lowest common multiple (LCM) of all the different clock periods, or an integer multiple of the LCM. To keep the SYSREF pulses periodic with respect to all the clocks, the SYSREF pulse needs to be latched with respect to the input clock with sufficient setup and hold margin. Once SYSREF is latched properly at the first flip-flop, it is much simpler to keep the latched SYSREF periodic inside the chip with respect to all the other clocks as the delay between SYSREF and all other clocks can be matched. As the device input clock frequency is set at higher and higher frequencies, it may become difficult to guarantee proper setup and hold margins across variations in process, voltage, and temperature (PVT) at the flip-flop that latches SYSREF. Further, if, for some reason, the SYSREF and device clock input to the chip are asynchronous, the periodicity of the latched SYSREF pulse cannot be guaranteed with respect to device clock.